The present invention relates, generally, to the fabrication of semiconductor devices and, more particularly, to the fabrication of complementary-metal-oxide-semiconductor (CMOS) device structures.
Conventional metal-oxide-semiconductor (MOS) transistor fabrication techniques utilize extension regions in the substrate on either side of the channel region below the gate electrode. The extension regions are generally aligned to the gate electrode and are doped at almost the same levels as that of the source/drain regions that are also formed in the substrate on either side of the extension regions. The extension regions function to reduce the electric field gradient in the channel region and minimize hot carrier injection into the gate oxide layer overlying the channel region.
As the gate length of an MOS transistor is reduced to about 0.1 microns or less, the more heavily doped source/drain regions can swamp the extension regions resulting in premature device failure. Attempts to solve the problem by simply increasing the lateral dimensions of the extension regions fail because the device will experience a substantial increase in parasitic resistance, which reduces the transistor drive current. Importantly, a high degree of activation of the extension regions and the doping and the transistor gate electrode are necessary to increase on-state current (Idsat). High resistance within the extension regions can increase the overall series resistance of the device and significantly reduce device saturation current (Idsat). Further, complete activation of dopant atoms in the extension regions requires relatively high-temperature thermal annealing. The high temperature processing causes dopant atoms in the substrate to diffuse, further increasing the series resistance of the device and degrading the rolloff of threshold voltage at short channel lengths.
One means of controlling the threshold voltage is to form a halo region in close proximity to the extension regions. The halo region has the same doping conductivity as that of the substrate in which the device is fabricated. Accordingly, the electrical characteristics of the substrate can be maintained, while increasing the activation levels of the extension regions and source/drain regions. However, the need for high-temperature thermal annealing to activate dopants also causes the halo regions to diffuse reducing their effectiveness.
In addition to the need to maintain a low series resistance in the transistor, many device applications require that the transistor have a stable threshold voltage. In particular, logic devices require that the threshold voltage of CMOS transistors be as constant as possible, regardless of the feature size of the transistors. The integrity of the halo region must be maintained in these devices to avoid changes in the threshold. However, the threshold voltage instability increases if the halo doping regions, individually formed in the vicinity of the source and drain regions, merge together as a result of lateral diffusion as the devices are scaled to smaller gate lengths. This problem can exist even at relatively large gate lengths. Additionally, lateral diffusion of the halo dopants changes the electrical characteristics of the channel region, which can lead to a reduction in the on-state electrical current in the channel region.
Simple geometric tailoring of the halo region doping profile has proven ineffective in the fabrication of MOS transistors having gate lengths on the order of 0.1 microns. The problem is particularly acute in the fabrication of N-channel devices that require boron implantation to fabricate the halo regions. Boron implantation is particularly problematic because boron has a relatively high penetration range (Rp) in silicon. Additionally, boron rapidly diffuses in a lateral direction once implanted into a silicon substrate. The lateral range, or straggle, of implanted boron makes the fabrication of precisely-configured boron profiles difficult. It is known that the lateral straggle of boron atoms can be reduced by reducing the implantation energy. However, for proper electrical performance, the boron halo region must be formed at relatively large depths within the silicon substrate. While it is desirable to have the reduced lateral straggle at low implantation energies, the halo regions must be deep enough to surround the extension regions within the substrate. Accordingly, advanced fabrication technology is necessary for the fabrication of high-functional MOS transistors having gate lengths on the order of about 0.1 micron and less.
The present invention is for a process for fabricating an MOS device having a highly-localized halo region. The process includes providing a semiconductor substrate having a first surface and a gate electrode structure disposed on the first surface. A first halo region is formed at the first surface adjacent to the gate electrode structure. A portion of the first surface is then removed to form a second surface and a second halo region is formed at the second surface. The first and second halo regions are formed, such that the first halo region is continuous with the second halo region.
In a more particular aspect of the invention, the first and second halo regions are formed by ion implantation of boron at an implant energy of no more than about 1 keV. In a non-limiting further aspect of the invention, the second halo region can be formed by implantation of boron at an angle of incidence that is offset with respect to the normal of the second surface.
In a more detailed aspect of the invention, the formation of the second surface is carried out by anisotropically etching the first surface, such that a wall surface is formed in the semiconductor substrate that connects the first surface and the second surface and that is substantially perpendicular to the first and second surfaces. The dimension of the wall surface can be adjusted depending upon the particular design characteristics of the MOS transistor being fabricated. Depending upon the length of the wall surface, the angled ion implantation of boron form the second halo region in conjunction with the formation of the second surface to ensure a uniform boron doping profile in the second halo region. The process can further include the formation of raised source/drain regions at the second surface.
In yet another aspect of the invention, processing is carried out to form a dielectric layer having a high dielectric constant or permittivity (xe2x80x9chigh-k dielectricxe2x80x9d) that functions as a gate dielectric layer and a MOS transistor. In the fabrication sequence, the originally-formed gate material is removed after completion of thermal activation annealing. Then, the high-capacitance dielectric material is formed and a second gate material is formed overlying the high-k dielectric material.
In yet another aspect of the invention, disposable sidewall spacers can be used to fabricate the source/drain regions, prior to the formation of the halo regions and other transistor components, such as the extension regions and the source/drain regions.
It will be appreciated that, for clarity of illustration, elements shown in the Figures are not necessarily drawn to scale. For example, the dimensions of the elements are exaggerated relative to each other for clarity. Further, when considered appropriate, reference numerals are repeated amongst the Figures to indicate corresponding elements.